The paper discusses source of error in the Controller Hardware-in-loop (CHIL) simulation of a physical Phase-Locked Loop (PLL) interfaced to the simulation of a Line-commutated Converter based HVdc transmission system. Sources of error investigated included interface delays, dc offsets and finite precision of A/D and D/A converters. In addition to actual CHIL simulation, an off-line EMT model was developed to model the simulation process itself by developing EMT models of interface equipment such as D/A and A/D converters. The results show that for the CHIL simulation of a PLL, a major factor affecting accuracy of the steady state quantities was the finite precision of the D/A and A/D converters, whereas delays and offsets in the expected range had marginal impact.
Y. Yi, A. D. Sinkar and A. M. Gole, "Effects of time delay, DC offset, and truncation errors on interfacing of a phase-locked loop (PLL) with a real-time simulator for controller hardware-in-loop (CHIL) simulation," 15th IET International Conference on AC and DC Power Transmission (ACDC 2019), Coventry, UK, 2019, pp. 1-5.
KEYWORDS: Phase-Locked Loop (PLL); Hardware-in-Loop (HIL) Simulation; LCC-HVdc