There is movement toward creating HVDC grids containing many HVDC terminals and employing Modular Multi-level Convertors (MMC). Each of the many convertors will typically include 6 valves. Each individual valve in a convertor can contain hundreds of Voltage Source Convertor (VSC) bridges of either the full or half bridge variety. Consequently, efficient simulation algorithms are required in order to be able to simulate these schemes in real-time using time-steps of 2 or 3 microseconds. This paper discusses simulation techniques that provide the required efficiency.
A surrogate network topology is described that represents the real valve behavior but requires significantly less computational power for simulation. First, a processor-based model is described. Subsequently, implementation details are provided for computing the model using the parallel hardware architecture of a Field Programmable Gate Array (FPGA). A single FPGA is used to model three separate valve models each containing 512 submodules (SMs). In order to demonstrate the accuracy of the proposed real-time methods, comparisons are provided between the results produced by the FPGA-based model, a simplified processor-based model calculated on the real-time simulator and
the simplified model implemented in PSCAD.
T. Maguire, B. Warkentin, Y. Chen, J. Hasler, Presented at the International Conference on Power Systems Transients (IPST2013) in Vancouver, Canada July 18-20, 2013. Paper #: 13IPST143
KEYWORDS: Modular multi-level converter, half-bridge, fullbridge, submodule, FPGA