This paper investigates in detail the impacts of distorted current waveforms, produced by certain types of fault current limiters on time-overcurrent protection relays. A thyristor-based solid-state fault current limiter is chosen as representative of such a device for a case study which investigates its effects on two coordinated protection relays. A detailed software model of the current limiter has been developed and implemented on the real-time digital simulator platform, modeling a typical distribution system. Relay models are used to obtain initial results, which are later validated by an actual protective relay connected in a hardware-in-the-loop simulation setup. The results illustrate the increase of relay tripping times due to severe current limitation caused by the fixed firing angle control of the current limiter. It is revealed that different current measurement principles employed by the relays, such as fundamental, peak, or true rms, can lead to miscoordination due to the distorted fault current waveform. It is demonstrated that these undesirable effects can be mitigated by employing appropriate control strategies for the firing angle in the current limiter.
Y. Pan, M. Steurer, T. L. Baldwin and P. G. McLaren, "Impact of Waveform Distorting Fault Current Limiters on Previously Installed Overcurrent Relays," in IEEE Transactions on Power Delivery, vol. 23, no. 3, pp. 1310-1318, July 2008, doi: 10.1109/TPWRD.2008.919170.
KEYWORDS: Distribution system, fault current limiter, grading margin, protection relay, real-time simulation.