The paper deals with the difficulties of testing firing pulse controls for a VSC-based HVDC scheme using a real time digital simulator. The main goal is to provide low latency, closed-loop interaction between the firing pulse controls and the simulator for PWM firing in the range of 1.6 kHz. The closed-loop setup is used to verify and improve the performance of the physical controls, so the simulator must provide an accurate representation of the actual VSC-based HVDC scheme for the full range of start-up, shut-down, steady state and transient operation.
The paper describes the difficulties encountered when attempting to test the actual firing pulse controls for a VSC-based HVDC link. The main difficulty resulted from the losses of the VSC converters in the simulation being higher than in the real system. To rectify the problem a new fixed topology 2-level
VSC was implemented using stored matrices to represent the different states of the converter.
In the final implementation, the power system circuit was split into four subnetworks each running in real time with a timestep < 3 μs. The real time simulation showed that the VSC losses in the simulation could match those of the real system. Furthermore the real time simulation results showed an excellent correlation with the results of off-line simulation.
P. Forsyth, T. Maguire, D. Shearer, D. Rydmell, Paper presented at IPST conference in Kyoto, Japan, June 2 - 6, 2009
KEYWORDS: VSC-based HVDC, real-time digital simulator, firing pulse controls, fixed topology VSC losses