FSU-CAPS recently purchased a 15 kV-class reconfigurable MW-scale PHIL amplifier named Optimus. This device consists of 2 Power Amplifier Units (PAUs) capable of producing voltages and/or currents in dc and ac modes up to 450 Hz. In the various configurations, the maximum current and voltage in ac 4-wire mode is 200 A at 17 kV (rms L-L) or 2.8 kArms at 1.2 kV (rms L-L). In dc mode, the maximum values are 200 A at 28 kV or 4 kA at 1 kV. Each PAU has 7 transformer isolated slices, making a total of 14 slices. Each slice comprises a set of three full H-bridge modules called cubes. These cubes have a nominal controllable DC link voltage of 1 kV with a 4 kHz PWM carrier active front end (AFE) and an inverter side (HB) interleaved effective switching frequency of 12 kHz. The Optimus can be controlled as a voltage source, with no current control loop or active balancing, or as a current source, following a direct-quadrature control scheme. The modularity, the controllability, and the relatively high switching frequency make this amplifier an excellent candidate for power hardware-in-the-loop (PHIL) applications.
Prior to delivery and installation of the Optimus amplifier, FSU-CAPS received all the necessary documentation and controller hardware to develop a full controller hardware-in-the-loop (CHIL) instantiation using RTDS as the real-time simulator of choice. This CHIL installation was to provide a platform to test and verify controls prior to, and during commissioning of the Optimus hardware in the lab. The CHIL simulation model was developed using one NovaCor with 10 active cores. The model of interest (MOI) was implanted in the sub-step environment in combination with the 2-level Universal Converter Model (UCM) and the improved firing pulse generator components. With the advent of the RTDS GTDIv2 I/O board, the MOI is provided with AFE and HB firing pulses from the controller boards. The controller feedback of voltage and current measurements are routed through RTDS GTAOv2 I/O boards. The CHIL model runs with a large time-step of 60 us and the substep hierarchies have a divisor of 9. To model all 7 slices of one PAU, one substep hierarchy contains at most 2 slices to model the AFE. While at most 4 slice HB fit into one substep hierarchy. The presentation provides a detailed description of the Optimus amplifier, CHIL instantiation, and validated commissioning results.
Mischa Steurer, Florida State University